1. Field of the Invention
The present invention relates to raised source/drain MOS transistors and, more particularly, to a raised source/drain MOS transistor and a method of forming the transistor with an implant spacer and an epitaxial spacer.
2. Description of the Related Art
A metal oxide semiconductor (MOS) transistor is a well-known semiconductor device which can be implemented as either an n-channel (NMOS) device or a p-channel (PMOS) device. A MOS transistor has spaced-apart source and drain regions, which are separated by a channel, and a gate that lies over, and is insulated from, the channel by a gate dielectric layer. A raised source/drain MOS transistor is a type of MOS transistor that also includes an epitaxially-grown raised source region and an epitaxially-grown raised drain region.
FIG. 1 shows a cross-sectional view that illustrates a prior-art raised source/drain MOS transistor 100. As shown in FIG. 1, MOS transistor 100 includes a semiconductor body 110. Semiconductor body 110, in turn, includes a single-crystal-silicon substrate region 112, and a trench isolation structure 114 that touches substrate region 112.
In addition, semiconductor body 110 includes a source 120 and a drain 122 that each touch substrate region 112. Source 120 includes a lightly-doped source region 120L, a heavily-doped source region 120H, and a raised source region 120E, each of which has a conductivity type that is the opposite of the conductivity type of substrate region 112.
Lightly-doped source region 120L touches substrate region 112, heavily-doped source region 120H touches both substrate region 112 and lightly-doped source region 120L, and raised source region 120E, which is heavily-doped, touches and lies above the top surface of heavily-doped source region 120H. Further, heavily-doped source region 120L has a maximum width W1 that is slightly, but insubstantially larger, than a maximum width W2 of raised source region 120E.
Similarly, drain 122 includes a lightly-doped drain region 122L, a heavily-doped drain region 122H, and a raised drain region 122E, each of which has a conductivity type that is the opposite of the conductivity type of substrate region 112. Lightly-doped drain region 122L touches substrate region 112, heavily-doped drain region 122H touches both substrate region 112 and lightly-doped drain region 122L, and raised drain region 122E touches and lies above the top surface of heavily-doped drain region 122H.
Further, heavily-doped drain region 122L has a maximum width W3 that is slightly, but insubstantially larger, than a maximum width W4 of raised drain region 122E. The source 120 and drain 122, which are spaced apart, also define a channel region 124 of substrate region 112. Channel region 124, which has the same conductivity type as substrate region 112, lies between source 120 and drain 122.
As further shown in FIG. 1, MOS transistor 100 includes a gate dielectric 126 that touches and lies over channel region 124, and a gate 130 that touches gate dielectric 126 and lies over channel region 124. MOS transistor 100 also includes a protective cap 131 that touches and lies over gate 130, and a sidewall spacer 132 that touches and laterally surrounds gate 130 and protective cap 131. Sidewall spacer 132, which is non-conductive, also touches the raised source and drain regions 120E and 122E.
The threshold voltage of a transistor is the gate voltage required to form an inversion layer at the top surface of the channel region that is sufficient to allow a current to flow from the source region to the drain region. In the case of an NMOS transistor, n-type dopant atoms form the inversion layer, while p-type dopant atoms form the inversion layer in the case of a PMOS transistor.
In operation, with respect to NMOS transistors, when a positive drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more positive than the threshold voltage, the NMOS transistor turns on and electrons flow from the source region to the drain region. When the gate-to-source voltage VGS is more negative than the threshold voltage, the MOS transistor turns off and no electrons (other than a very small leakage current) flow from the source region to the drain region.
With respect to PMOS transistors, when a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, the PMOS transistor turns on and holes flow from the source region to the drain region. When the gate-to-source voltage VGS is more positive than the threshold voltage, the PMOS transistor turns off and no holes (other than a very small leakage current) flow from the source region to the drain region.
One issue that becomes increasingly important as transistor sizes shrink to, for example, a 50 nm-size, is short channel effects. One approach to controlling short channel effects in conventional 50 nm-sized transistors, which do not have raised source and drain regions, is to utilize very shallow junctions. Very shallow junctions, however, increase the series resistance of the source and the drain. One technique for reducing the series resistance is to reduce the width of the sidewall spacer.
However, when the width of the sidewall spacer is meaningfully reduced, the out diffusion of dopant atoms from the heavily-doped source and drain regions during an anneal commonly consumes and eliminates the lightly-doped source and drain regions which, in turn, reduces the short channel performance.
Raised source/drain MOS transistor 100 differs from conventional 50 nm-sized transistors in that the raised source and drain regions 120E and 122E substantially reduce the number of dopant atoms from the heavily-doped source and drain regions 120H and 122H that diffuse during the anneal into the lightly-doped source and drain regions 120L and 122L that lie below sidewall spacer 132.
Thus, MOS transistor 100 improves short channel performance because a thin sidewall spacer, which improves short channel performance, is used in combination with the raised source and drain regions 120E and 122E, which limit the diffusion of dopant atoms into the lightly-doped source and drain regions 120L and 122L, and thereby prevent the lightly-doped source and drain regions 120L and 122L from being consumed.
FIGS. 2A-2F show cross-sectional views that illustrate a prior-art method 200 of forming a raised source/drain MOS transistor. As shown in FIG. 2A, method 200 utilizes a conventionally-formed semiconductor body 210 that includes a single-crystal-silicon substrate region 212 and an isolation structure 214 that touches substrate region 212. As further shown in FIG. 2, method 200 begins by forming a gate dielectric layer 216 that touches and lies over substrate region 212. Gate dielectric layer 216 can be implemented with, for example, a layer of oxide.
After gate dielectric layer 216 has been formed, a gate layer 218 is formed to touch and lie over gate dielectric layer 216. Gate layer can be implemented with, for example, a layer of polysilicon. Once gate layer 218 has been formed, a protective layer 219 is formed to touch and lie over gate layer 218. Protective layer 219 can be implemented with, for example, a layer of nitride. Following this, a patterned mask 220 is formed on protective layer 218 using conventional procedures.
As shown in FIG. 2B, after patterned mask 220 has been formed, the exposed regions of protective layer 219, underlying gate layer 218, and underlying gate dielectric layer 216 are etched away in a conventional manner to expose the top surface of substrate region 212 and form a gate structure 221.
Gate structure 221, in turn, includes a gate dielectric 222 that touches and lies above substrate region 212, a gate 224 that touches and lies above gate dielectric 222, and a protective cap 225 that touches and lies above gate 224. Following the etch, patterned mask 220 is removed in a conventional manner.
As shown in FIG. 2C, after patterned mask 220 has been removed, a dopant is implanted into substrate region 212 using conventional procedures, followed by an anneal to drive in the implant and form spaced-apart lightly-doped regions 230 and 232. The lightly-doped regions 230 and 232 have a conductivity type that is opposite to the conductivity type of substrate region 212.
As shown in FIG. 2D, after the lightly-doped regions 230 and 232 have been formed, a non-conductive side wall spacer 234 is formed in a conventional fashion to touch and laterally surround gate 224 and protective cap 225. Non-conductive side wall spacer 234 can be formed in a number of ways. For example, a layer of oxide can be deposited on gate 224, protective cap 225, lightly-doped source region 230, and lightly-doped drain region 232, followed by the anisotropic etch of the layer of oxide until the top surface of protective cap 225 has been exposed to form sidewall spacer 234.
As shown in FIG. 2E, after side wall spacer 234 has been formed, a raised source region 240 is epitaxially grown on lightly-doped source region 230, while a raised drain region 242 is epitaxially grown on lightly-doped drain region 232 at the same time. Nothing is epitaxially grown on gate 224 due to the presence of protective cap 225.
As shown in FIG. 2F, after the raised source region 240 and the raised drain region 242 have been formed, a dopant is implanted into substrate region 212 and the lightly-doped regions 230 and 232 to form spaced-apart heavily-doped source and drain regions 244 and 246. Raised source region 240 and raised drain region 242 are also doped during the implant.
Following the implant raised source region 240 and heavily-doped source region 244 have substantially equal maximum widths. Similarly, after the implant raised drain region 242 and heavily-doped drain region 246 have substantially equal maximum widths. Further, the raised source and drain regions 240 and 242 and the heavily-doped source and drain regions 244 and 246 each have a conductivity type that is opposite to the conductivity type of substrate region 212.
Lightly-doped source region 230, raised source region 240, and heavily-doped source region 244 form a source 250, while lightly-doped drain region 232, raised drain region 242, and heavily-doped region 246 form a drain 252. The source and drain 250 and 252 define a channel region 254 of substrate region 212 that lies between and separates the source and drain 250 and 252. Further, the implant also forms a MOS transistor structure 260.
Following this, MOS transistor structure 260 is again annealed to drive in the implant. The anneal causes the heavily-doped source and drain regions 244 and 246 to expand slightly into the lightly-doped source and drain regions 230 and 232 due to out diffusion. As a result, the maximum width of heavily-doped source region 244 is slightly larger than the maximum width of raised source region 240.
However, since the only difference in the maximum widths is due to out diffusion, the maximum width of heavily-doped source region 244 is insubstantially larger than the maximum width of raised source region 240. Similarly, the maximum width of heavily-doped drain region 246 is slightly larger than the maximum width of raised drain region 242 due to out diffusion. However, since the only difference in the maximum widths is due to out diffusion, the maximum width of heavily-doped drain region 246 is insubstantially larger than the maximum width of raised drain region 242. Following this, method 200 continues with conventional steps.
FIGS. 3A-3B show cross-sectional views that illustrate an alternate prior-art method 300 of forming a raised source/drain MOS transistor. Method 300 is similar to method 200 and, as a result, utilizes the same reference numerals to designate the structures that are common to both methods.
Method 300 is the same as method 200 up through the formation of sidewall spacer 234 shown in FIG. 2D, and differs from method 200 in that, as shown in FIG. 3A, method 300 next implants a dopant into substrate region 212 and the lightly-doped source and drain regions 230 and 232 to form spaced-apart heavily-doped source and drain regions 310 and 312.
As shown in FIG. 3B, after the heavily-doped source and drain regions 310 and 312 have been formed, a raised source region 320 is epitaxially grown on heavily-doped source region 310, while a raised drain region 322 is epitaxially grown on heavily-doped drain region 312 at the same time.
Lightly-doped source region 230, raised source region 320, and heavily-doped source region 310 form a source 330, while lightly-doped drain region 232, raised drain region 322, and heavily-doped drain region 312 form a drain 332. The source and drain regions 330 and 332 form a channel region 334 in substrate region 212 that lies between and separates the source and drain regions 330 and 332. Further, the implant also forms a MOS transistor structure 340.
Following this, MOS transistor structure 340 is again annealed to drive in the heavily-doped implant. The anneal causes the heavily-doped source and drain regions 310 and 312 to expand slightly into the lightly-doped source and drain regions 230 and 232 due to out diffusion. As a result, the maximum width of heavily-doped source region 310 is slightly, but insubstantially larger, than the maximum width of raised source region 320. Similarly, the maximum width of heavily-doped drain region 312 is slightly, but insubstantially larger, than the maximum width of raised drain region 322. Following this, method 300 continues with conventional steps.
Although method 200 and method 300 illustrate approaches for fabricating a raised source/drain MOS transistor, there is a need for additional approaches to fabricating raised source/drain MOS transistors.